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CS4970X4 Datasheet(PDF) 8 Page - Cirrus Logic

Part No. CS4970X4
Description  32-bit High Definition Audio Decoder DSP Family
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4970X4 Datasheet(HTML) 8 Page - Cirrus Logic

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Copyright 2008 Cirrus Logic
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock
domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads
the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be
sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates
from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of
the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together
into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz SPDIF transmitter
(data with embedded clock on a single line).
4.2.3 Serial Control Port 1 & 2 (I2C® or SPI)
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes.
SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50
MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults
to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control.
4.2.4 Parallel Control Port
The CS4970x4 parallel port supports both Motorola® and Intel® interfaces. It can be used for both control and data
delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package.
4.2.5 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.6 GPIO
Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an
input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low,
or active-high.
4.2.7 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the
DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference frequency
and can be switched to use the PLL output after overlays have been loaded and configured, either through master
boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is
provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4
System Designer’s Guide.
4.3.2 Termination Requirements
Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4 System
Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper

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