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CS4970X4 Datasheet(PDF) 7 Page - Cirrus Logic

Part No. CS4970X4
Description  32-bit High Definition Audio Decoder DSP Family
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com

CS4970X4 Datasheet(HTML) 7 Page - Cirrus Logic

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Copyright 2008 Cirrus Logic
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
4. Hardware Functional Description
4.1 DSP Core
The CS4970x4 is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-
performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory access control
(MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and
12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such
as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all
without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving
more MIPS available for signal processing instructions.
CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to the
CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio decoder and
post-processor modules which are available from Cirrus Logic.
The CS4970x4 is suitable for Audio Decoder, Audio Post-processor, Audio Encoder, DVD Audio/Video Player, and
Digital Broadcast Decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory for any
of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and
THX Ultra2. However, if the end-system design requires support of the new high-definition audio formats, external
SDRAM will be needed to support Dolby TrueHD and DTS-HD Master Audio.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own
arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the
peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment
controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting
PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and
internally converted to PCM before processing. Additionally support is provided for audio data input to the DSP via
the DAI from an HDMI receiver.
Table 3. CS4970x4 DSP Memory Sizes
16k SRAM, 32k ROM
10k SRAM, 8k ROM
24k SRAM, 32k ROM
16k SRAM, 16k ROM
8k SRAM, 32k ROM
8k SRAM, 24k ROM

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