Electronic Components Datasheet Search |
|
CDB4382A Datasheet(PDF) 6 Page - Cirrus Logic |
|
CDB4382A Datasheet(HTML) 6 Page - Cirrus Logic |
6 / 50 page 6 DS618F1 CS4382A 1. PIN DESCRIPTION Pin Name # Pin Description VD 4 Digital Power (Input) - Positive power supply for the digital section. GND 5 31 Ground (Input) - Ground reference. Should be connected to analog ground. MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. LRCK 7 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. SDIN1 SDIN2 SDIN3 SDIN4 8 11 13 14 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface. VLC 18 Control Port Power (Input) - Determines the required signal level for the Control Port. Refer to the Recommended Operating Conditions for appropriate voltages. RST 19 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram. VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to bias the analog circuitry assuming there is no AC signal component and the DC current is less than the maximum specified in the Analog Characteristics and Specifications section. MUTEC1 MUTEC234 41 22 Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. GND AOUTB2- AOUTA3+ AOUTB3- AOUTB2+ VA AOUTA3- AOUTB3+ AOUTA4- AOUTA4+ 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 MCLK DSDB1 VD SDIN1 TST DSDA2 DSDA1 GND SCLK SDIN2 TST LRCK(DSD_EN) CS4382A AOUTA2+ AOUTA2- |
Similar Part No. - CDB4382A |
|
Similar Description - CDB4382A |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |