Electronic Components Datasheet Search |
|
CS2000-OTP Datasheet(PDF) 22 Page - Cirrus Logic |
|
CS2000-OTP Datasheet(HTML) 22 Page - Cirrus Logic |
22 / 30 page CS2000-OTP 22 DS758PP1 5.8.2 PLL Unlock Conditions Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked: • Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new setting takes affect. • Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101, or 110 can cause the PLL to temporarily lose lock as the new setting takes affect. • Any discontinuities on the Timing Reference Clock, REF_CLK. • Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page 11). • Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency. • Step changes in CLK_IN frequency. |
Similar Part No. - CS2000-OTP |
|
Similar Description - CS2000-OTP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |