CS2000-CP

14

DS761PP1

5.1.3

External Reference Clock (REF_CLK)

For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the

reference clock source and XTO should be left unconnected or pulled low through a 47 k

Ω resistor to

GND.

5.2

Frequency Reference Clock Input, CLK_IN

The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and Fractional-

N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid An-

alog-Digital PLL” on page 12). The Digital PLL first compares the CLK_IN frequency to the PLL output. The

Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal

timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock

which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference

clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Char-

acteristics” on page 8.

5.2.1

CLK_IN Frequency Detector

The CLK_IN frequency range detector determines and indicates the ratio between the frequency of the

internal SysClk and the CLK_IN input signal.

The result of the ratio measurement is available in the read-only FsDet[1:0] bits and is also used by the

device to determine the Auto R-Mod value.

Table 1. PLL Input Clock Range Indicator

ticularly useful when used in conjunction with the Auto R-Mod feature (see section 5.3.4 on page 18)

.

5.2.2

CLK_IN Skipping Mode

CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses

skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn bit enables

this function.

to 1048 ms) after CLK_IN is removed (see Figure 9). This is true as long as CLK_IN does not glitch or

have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as

pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock

Output” on page 22. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified

FsDetect[1:0]

00

> 224

01

96 - 224

10

< 96

11

Reserved

Referenced Control

Register Location

FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 27