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PDI1284P11DL Datasheet(PDF) 4 Page - NXP Semiconductors |
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PDI1284P11DL Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 16 page PDI1284P11_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 25 August 2008 4 of 16 NXP Semiconductors PDI1284P11 3.3 V parallel interface transceiver/buffer 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 2. Pin configuration PDI1284P11 HD DIR A9 Y9 A10 Y10 A11 Y11 A12 Y12 A13 Y13 VCC VCC(B) A1 B1 A2 B2 GND GND A3 B3 A4 B4 A5 B5 A6 B6 GND OEA A7 B7 A8 B8 VCC VCC(B) PLHI PLHO A14 C14 A15 C15 A16 C16 A17 C17 HLHO HLHI 001aai291 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Table 2. Pin description Symbol Pin Description HD 1 high drive enable/disable input A1 to A8 8, 9, 11, 12, 13, 14, 16, 17 data input/output B1 to B8 41, 40, 38, 37, 36, 35, 33, 32 IEEE 1284 standard output/input[1] A9 to A13 2, 3, 4, 5, 6 data input Y9 to Y13 47, 46, 45, 44, 43 IEEE 1284 standard output[1] C14 to C17 29, 28, 27, 26 control input (cable)[1] A14 to A17 20, 21, 22, 23 control output (peripheral) VCC 7, 18 supply voltage GND 10, 15, 39 ground (0 V) PLHI 19 peripheral logic high input (peripheral) |
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