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PCK953BD Datasheet(PDF) 4 Page - NXP Semiconductors |
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PCK953BD Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 15 page PCK953_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 9 October 2008 4 of 15 NXP Semiconductors PCK953 20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver 7. Limiting values 8. Static characteristics [1] Vcm is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the Vcm range and the input swing lies within the Vi(p-p) specification. [2] The PCK953 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to 0.5V CC) transmission lines on the incident edge (see Section 11 “Application information”). Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.3 +4.6 V VI input voltage −0.3 VDD + 0.3 V II input current - ±20 mA Tstg storage temperature −40 +125 °C Table 5. Static characteristics Tamb =0 °C to 70 °C; VCC = 3.3 V ± 5 %, unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage LVCMOS inputs 2.0 - 3.6 V VIL LOW-level input voltage LVCMOS inputs - - 0.8 V Vi(p-p) peak-to-peak input voltage PECL_CLK 300 - 1000 mV Vcm common-mode voltage PECL_CLK [1] VCC − 1.5 - VCC − 0.6 mV VOH HIGH-level output voltage IOH = −20 mA [2] 2.4 - - V VOL LOW-level output voltage IOL =20mA [2] - - 0.5 V II input current - - ±75 µA Ci input capacitance - - 4 pF CPD power dissipation capacitance per output - 25 - pF ICC maximum quiescent supply current all VCC pins - 9 20 mA ICCPLL maximum PLL supply current VCCA pin only - 9 20 mA |
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