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AT88SC6416C-PU Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT88SC6416C-PU Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 18 page  5 5015HS–SMEM–11/08 AT88SC6416C Figure 3. Bus Timing for 2 wire communications SCL: Serial Clock, SDA: Serial Data I/O Figure 4. Write Cycle Timing: SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 5. Data Validity t WR (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT SCL SDA DATA CHANGE ALLOWED |
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