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P89LPC936FDH Datasheet(PDF) 10 Page - NXP Semiconductors |
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P89LPC936FDH Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 75 page P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 10 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 11 “Static characteristics” for details. All pins have Schmitt trigger inputs. Port 3 also provides various special functions as described below: P3.0/XTAL2/ CLKOUT 9 5 I/O P3.0 — Port 3 bit 0. O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer. P3.1/XTAL1 8 4 I/O P3.1 — Port 3 bit 1. I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. VSS 73I Ground: 0 V reference. VDD 21 17 I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Table 4. Pin description …continued Symbol Pin Type Description TSSOP28, PLCC28 HVQFN28 |
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