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P89V660_0811 Datasheet(PDF) 69 Page - NXP Semiconductors |
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P89V660_0811 Datasheet(HTML) 69 Page - NXP Semiconductors |
69 / 89 page P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 69 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI 6.13.1 Idle mode Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program counter is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode. The device exits Idle mode through either a system interrupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode. A hardware reset starts the device similar to a power-on reset. 6.13.2 Power-down mode The Power-down mode is entered by setting the PD bit in the PCON register. In the Power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during Power-down, the minimum VDD level is 2.0 V. The device exits Power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked Power-down mode. A hardware reset starts the device similar to power-on reset. To exit properly out of Power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). Table 67. Power-saving modes Mode Initiated by State of MCU Exited by Idle mode Software (Set IDL bit in PCON) MOV PCON, #01H CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN signals at a HIGH-state during Idle. All registers remain unchanged. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction, program resumes execution beginning at the instruction following the one that invoked Idle mode. A hardware reset restarts the device similar to a power-on reset. Power-down mode Software (Set PD bit in PCON) MOV PCON, #02H CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN signals at a LOW-state during power-down. External Interrupts are only active for level sensitive interrupts, if enabled. Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power-down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power-down mode. A hardware reset restarts the device similar to a power-on reset. |
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