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29C516E Datasheet(PDF) 8 Page - ATMEL Corporation |
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29C516E Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 17 page  29C516E 8 Rev. E (03 2007) Table 6: Single Bit–Error MD [..] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] SY(hexa) 34h 2Ah 29h 25h 32h 1Ah 16h 13h 31h 23h 15h 0Bh 2Ch 1Ch 0Eh 0Dh MC [..] [–] [–] [5] [4] [3] [2] [1] [0] SY(hexa) ––h ––h 20h 10h 08h 04h 02h 01h 7.3. Double–Bit Error If two errors occurs, there will be either 2, 4 or 6 bits set to one in the syndrome byte. The syndrome value generated by a double–bit error does not take place of a syndrome value generated by a single–bit error. Then, only the non correctable error flag NCERR will be activated to indicate that errors are present but cannot be corrected. Example: If MD[4] and MC[2] are incorrect, syndrome bits [0], [1], [2] and [3] are set to one (SY=0Fh ), NCERR is set low and CERR remains at high level. 7.4. Triple–Bit Error Triple–Bit Error When three errors are detected, an error flag is set low as warning to the system. But the generated syndrome can have the listed value of single–bit error. The device must be in detect mode to prevent false correction occurring. Example: If MD[0], MD[14] and MC[1] are corrupted, the syndrome value is ”25h ”. This is decoded by the 29C516E EDAC as being a correctable error on MD[12]. The CERR flag is set low and correction would take place if the device is in correct mode. This would cause more errors. 7.5. 4–bit Wide Memory Error The 6 check–bit code can be used to provide error detection for up to 4 errors occurring in the following groups: MD[15..12], MD[11..8], MD[7..4], MD[3..0], MC[5..3] and MC[2..0]. The 29C516E EDAC can flag any number of errors in 4–bit wide memory chip. A special attention must be taken, multi–bit error ( 3) located into the defined groups can provide the syndrome byte of a single–bit error. Example: If MD[3], MD[2], MD[1] and MD[0] are in error, the syndrome code is ”33 h ”; 8. The 8–Bit Syndrome Word This feature is available when the N22 pin is driven at a low level. 8.1. No Errors If there are no errors in the read Data or Check–Bit, all the syndrome byte is ”00”. The EDAC flags are inactive. No Error : SY=00 8.2. Single Bit–Error Single Bit–Error A single bit–error in a Memory Data word read (MD[..]) causes three syndrome bits to be set to one. The code formed indicates which bit of the Memory Data word is incorrect. For example, if MD[10] were incorrect, the syndrome byte would have bits 1, 3 and 4 set to one. The syndrome decoder of 29C516E EDAC decodes the information in the syndrome byte and only sets low the error flag CERR. In correct mode (CORRECT pin active), it inverts (and hence corrects) the relevant bit in error of the Memory Data word and provides the expected Data word for the EDAC controller. If there is an error in the Memory Check–bit (MC[..]), only one bit of the syndrome is set to one. In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR does not change. It does not correct the Check–bit because these bits are not used by the system. |
Similar Part No. - 29C516E_07 |
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Similar Description - 29C516E_07 |
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