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ISP1512AUK Datasheet(PDF) 11 Page - NXP Semiconductors

Part # ISP1512AUK
Description  ULPI Hi-Speed USB transceiver
Download  56 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

ISP1512AUK Datasheet(HTML) 11 Page - NXP Semiconductors

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ISP1512A_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 31 July 2008
10 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
to t3 for greater than tw(REG1V8_L), another POR pulse is generated. If the dip from t4 to t5
is less than tw(REG1V8_L), the internal POR pulse will not be generated and will remain
LOW.
8.10 Detailed description of pins
8.10.1 DATA[7:0]
Bidirectional data bus pins. The USB link must drive DATA[7:0] to LOW when the ULPI bus
is idle. When the link has data to transmit to the PHY, it drives a nonzero value. Weak
pull-down resistors are incorporated into DATA[7:0] pins as part of the interface protect
feature.
DATA[7:0] pins can also be 3-stated when pin CHIP_SEL is deasserted.
The data bus can be reconfigured to carry various data types. For details, see Section 9.2.
8.10.2 VCC(I/O)
The input power pin that sets the I/O voltage level. A 0.1
µF decoupling capacitor is
recommended on this pin.
8.10.3 RREF
Resistor reference analog I/O pin. A 12 k
Ω± 1 % resistor must be connected between the
RREF pin and GND. This provides an accurate voltage reference that biases the internal
analog circuitry. Less accurate resistors cannot be used and will render the ISP1512A
unusable.
8.10.4 DP and DM
When the ISP1512A is in USB mode, the DP pin functions as the USB data plus line, and
the DM pin functions as the USB data minus line.
When the ISP1512A is in transparent UART mode, the DP pin functions as the UART
RXD input pin, and the DM pin functions as the UART TXD output pin.
The DP and DM pins must be connected to the D+ and D
− pins of the USB receptacle.
8.10.5 VCC
Main input supply voltage for the ISP1512A. The ISP1512A operates correctly when VCC
is between 3.0 V and 4.5 V. A 0.1
µF decoupling capacitor is recommended.
Fig 3.
Internal power-on reset timing
004aab023
REG1V8
t0
t1
t2
t3
t4
t5
VPOR(trip)
POR


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