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ADC0808S250 Datasheet(PDF) 10 Page - NXP Semiconductors |
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ADC0808S250 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 23 page ADC0808S125_ADC0808S250_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 October 2008 10 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 8. Limiting values 9. Thermal characteristics [1] In compliance with JEDEC test board, in free air. 10. Static characteristics Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCCA analog supply voltage −0.5 +4.6 V VCCD digital supply voltage −0.5 +2.5 V VCCO output supply voltage −0.5 +2.5 V Vi(IN) input voltage on pin IN referenced to AGND −0.5 VCCA +1 V Vi(INN) input voltage on pin INN referenced to AGND −0.5 VCCA +1 V Vi(CLK) input voltage on pin CLK referenced to DGND −0.5 VCCD + 0.55 V Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C Table 11. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient [1] 36.2 K/W Rth(j-c) thermal resistance from junction to case [1] 14.3 K/W Table 12. Static characteristics VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD =VCCO = 1.8 V, Tamb =25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCA analog supply voltage 3.0 3.3 3.6 V VCCD digital supply voltage 1.65 1.80 1.95 V VCCO output supply voltage 1.65 1.80 1.95 V ICCA analog supply current fclk = 125 MHz; fi = 1.25 MHz - 60 - mA ICCD digital supply current fclk = 125 MHz; fi = 1.25 MHz - 12 - mA ICCO output supply current fclk = 125 MHz; fi = 1.25 MHz - 11 - mA Ptot total power dissipation fclk = 125 MHz; fi = 1.25 MHz - 240 - mW Clock inputs: pins CLK+ and CLK − Ri input resistance [1] -10 - k Ω Ci input capacitance [1] -1 - pF LVDS clock input; see Figure 3 ∆VI input voltage range VI on pin CLK+ or CLK−; |Vgpd|<50mV [2] 825 - 1575 mV |
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