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DAC8411IDCKTG4 Datasheet(PDF) 5 Page - Texas Instruments |
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DAC8411IDCKTG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 40 page PIN CONFIGURATION 1 2 3 6 5 4 SYNC SCLK D IN V OUT GND AV /V DD REF DAC8311 DAC8411 www.ti.com ................................................................................................................................................................................................ SBAS439 – AUGUST 2008 DCK PACKAGE SC70-6 (TOP VIEW) Table 1. PIN DESCRIPTION PIN NAME DESCRIPTION Level-triggered control input (active low). This is the frame sychronization signal for the input data. When SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle, 1 SYNC unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt sections for more details. 2 SCLK Serial Clock Input. Data can be transferred at rates up to 50MHz. Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on 3 DIN the falling edge of the serial clock input. 4 AVDD/VREF Power Supply Input, +1.8V to 5.5V. 5 GND Ground reference point for all circuitry on the part. 6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): DAC8311 DAC8411 |
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