CY23S08
3.3V Zero Delay Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07265 Rev. *H
Revised November 3, 2008
Features
■ Zero input output propagation delay, adjustable by capacitive
load on FBK input
■ Multiple configurations (see Table 3 on page 3)
■ Multiple low-skew outputs
❐ 45 ps typical output-output skew (–1)
❐ Two banks of four outputs, three-stateable by two select in-
puts
■ 10 MHz to 140 MHz operating range
■ 65 ps typical cycle-cycle jitter (–1, –1H)
■ Advanced 0.65μ CMOS technology
■ Space saving 16-pin, 150-mil SOIC/TSSOP packages
■ 3.3V operation
■ Spread Aware
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback must be driven into
the FBK pin, and obtained from one of the outputs. The
input-to-output propagation delay is less than 350 ps, and
output-to-output skew is less than 250 ps.
The CY23S08 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in Table 2 on page 3. If
all output clocks are not required, Bank B can be three-stated.
The select inputs also enable the input clock to be directly
applied to the output for chip and system testing purposes.
The CY23S08 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50
μA of current draw. The PLL shuts down in two additional
cases as shown in Table 2 on page 3.
Multiple CY23S08 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY23S08 is available in five different configurations, as
shown in Table 3 on page 3. The CY23S08–1 is the base part,
where the output frequencies equal the reference if there is no
counter in the feedback path. The CY23S08–1H is the high drive
version of the –1, and rise and fall times on this device are much
faster.
The CY23S08–2 enables the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the feedback
pin. The CY23S08–2H is the high drive version of the –2, and
rise and fall times on this device are much faster.
The CY23S08–3 enables the user to obtain 4X and 2X
frequencies on the outputs.
The CY23S08–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is versatile, and can be used in a variety
of applications.
Logic Block Diagram
REF
CLKA1
CLKA2
CLKA3
CLKA4
FBK
PLL
MUX
Select Input
Decoding
S2
S1
CLKB1
CLKB2
CLKB3
CLKB4
/2
Extra Divider (–2, –2H, –3)
/2
Extra Divider (–3, –4)
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