CY29976
Document #: 38-07413 Rev. *B
Page 6 of 9
Power Management
The individual output enable/freeze control of the CY29976
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic ‘0’
state when the freeze control bits are activated. The serial input
register contains one programmable freeze enable bit for 12 of
the 14 output clocks. The QC0 and FB_OUT outputs can not be
frozen with the serial port, this avoids any potential lock up
situation must an error occur in the loading of the serial data. An
output is frozen when a logic ‘0’ is programmed and enabled
when a logic ‘1’ is written. The enabling and freezing of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
The serial input register is programmed through the SDATA input
by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable
bits. The period of each SDATA bit equals the period of the free
running SCLK signal. The SDATA is sampled on the rising edge
of SCLK.
Figure 2. Control Bit Map
Maximum Ratings[3]
Input Voltage Relative to VSS: ............................. VSS – 0.3V
Input Voltage Relative to VDD: ............................. VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum Power Supply:................................................ 5.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout must be constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
DC Parameters V
DD = VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min
Typ.
Max
Unit
VIL
Input Low Voltage
VSS
0.8
V
VIH
Input High Voltage
2.0
VDD
V
VPP
Peak-to-Peak Input Voltage PECL_CLK
Note 4
300
1000
mV
VCMR
Common Mode Range PECL_CLK
VDD – 2.0
VDD – 0.6
V
IIL
Input Low Current (at VIL = VSS)
Note 5
–120
µA
IIH
Input High Current (at VIH = VDD)
Note 5
120
µA
VOL
Output Low Voltage
IOL = 20 mA, Note 6
0.5
V
VOH
Output High Voltage
IOH = –20 mA, Note 6
2.4
V
IDDC
Quiescent Supply Current
All VDDC and VDD
10
15
mA
IDD
PLL Supply Current
VDD only
15
mA
Cin
Input Pin Capacitance
4
pF
Notes
3. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply srquencing is NOT required.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when “High” input is within the VCMR range and the
input lies within the VPP specification.
5. Inputs have pull up/pull down resistors that effect input current.
6. Driving series or parallel terminated 50
Ω (or 50Ω to V
DD/2) transmission lines.
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