CY2308
Document Number: 38-07146 Rev. *F
Page 3 of 14
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Available CY2308 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY2308–1
Bank A or Bank B
Reference
Reference
CY2308–1H
Bank A or Bank B
Reference
Reference
CY2308–2
Bank A
Reference
Reference/2
CY2308–2
Bank B
2 X Reference
Reference
CY2308–3
Bank A
2 X Reference
Reference or Reference[5]
CY2308–3
Bank B
4 X Reference
2 X Reference
CY2308–4
Bank A or Bank B
2 X Reference
2 X Reference
CY2308–5H
Bank A or Bank B
Reference /2
Reference /2
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins
Note
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
[+] Feedback