CY22392
Document #: 38-07013 Rev. *E
Page 5 of 9
Switching Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
1/t1
Output Frequency[3, 4]
Clock output limit, Commercial
–
–
200
MHz
Clock output limit, Industrial
–
–
166
MHz
t2
Output Duty Cycle[3, 5]
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured at VDD/2
45%
50%
55%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured at VDD/2
40%
50%
60%
t3
Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t4
Falling Edge Slew
Rate[3]
Output clock fall time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t5
Output three-state
Timing[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t6
Clock Jitter[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at VDD/2
–400
–
ps
t7
Lock Time[3]
PLL Lock Time from Power up
–
1.0
3
ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
Figure 3. Output Three-State Timing
Figure 4. CLK Output Jitter
Notes
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
t1
OUTPUT
t2
t3
t4
t5
OE
ALL
OUTPUTS
t5
THREE-STATE
CLK
OUTPUT
t6
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