Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CY2291 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part No. CY2291
Description  Three-PLL General Purpose EPROM Programmable Clock Generator
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
Logo 

CY2291 Datasheet(HTML) 7 Page - Cypress Semiconductor

Zoom Inzoom in Zoom Outzoom out
 7 / 12 page
background image
CY2291
Document #: 38-07189 Rev. *C
Page 7 of 12
t10B
Lock Time for
UPLL and SPLL
Lock Time from Power Up
< 0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2291
8
100
MHz
CY2291F
8
90
MHz
Switching Characteristics, Commercial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 3.3V
operation
CY2291
12.5
(80 MHz)
13000
(76.923 kHz)
ns
CY2291F
15
(66.6 MHz)
13000
(76.923 kHz)
ns
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1
[12]
fOUT > 66 MHZ
40%
50%
60%
Duty cycle for outputs, defined as t2 ÷ t1
[12]
fOUT < 66 MHZ
45%
50%
55%
t3
Rise Time
Output clock rise time[13]
35
ns
t4
Fall Time
Output clock fall time[13]
2.5
4
ns
t5
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
10
15
ns
t6
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
ns
t7
Skew
Skew delay between any identical or related outputs[3,
12, 15]
< 0.25
0.5
ns
t8
CPUCLK Slew
Frequency transition rate
1.0
20.0
MHz/m
s
t9A
Clock Jitter[14]
Peak-to-peak period jitter (t9A Max. – t9A min.),% of
clock period (fOUT < 4 MHz)
<0.5
1
%
t9B
Clock Jitter[14]
Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz
< fOUT < 16 MHz)
<0.7
1
ns
t9C
Clock Jitter[14]
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
<400
500
ps
t9D
Clock Jitter[14]
Peak-to-peak period jitter
(fOUT > 50 MHz)
<250
350
ps
t10A
Lock Time for
CPLL
Lock Time from Power Up
<25
50
ms
t10B
Lock Time for
UPLL and SPLL
Lock Time from Power Up
<0.25
1
ms
Slew Limits
CPU PLL Slew Limits
CY2291
8
80
MHz
CY2291F
8
66.6
MHz
Switching Characteristics, Commercial 5.0V (continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
[+] Feedback


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn