CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *L
Page 11 of 46
8.1 68-Pin Part Pinout (On-Chip Debug)
The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 8-4. 68-Pin Part Pinout (QFN[4])
Pin
No.
Type
Name
Description
Figure 8-4. CY8C24094 68-Pin OCD PSoC Device
Digital Analog
1
IO
M
P4[7]
2
IO
M
P4[5]
3
IO
MP4[3]
4
IO
MP4[1]
5
OCDE OCD even data IO.
6
OCDO OCD odd data output.
7
Power
Vss
Ground connection.
8
IO
M
P3[7]
9
IO
M
P3[5]
10
IO
MP3[3]
11
IO
MP3[1]
12
IO
M
P5[7]
13
IO
M
P5[5]
14
IO
MP5[3]
15
IO
MP5[1]
16
IO
M
P1[7]
I2C Serial Clock (SCL).
17
IO
M
P1[5]
I2C Serial Data (SDA).
18
IO
M
P1[3]
19
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP SCLK[3].
20
Power
Vss
Ground connection.
21
USB
D+
22
USB
D-
23
Power
Vdd
Supply voltage.
24
IO
P7[7]
25
IO
P7[6]
26
IO
P7[5]
27
IO
P7[4]
28
IO
P7[3]
29
IO
P7[2]
Pin
No.
Type
Name
Description
30
IO
P7[1]
Digital Analog
31
IO
P7[0]
50 IO
M
P4[6]
32
IO
M
P1[0]
I2C Serial Data (SDA), ISSP SDATA[3].51 IO
I,M
P2[0]
Direct switched capacitor block input.
33
IO
M
P1[2]
52 IO
I,M
P2[2]
Direct switched capacitor block input.
34
IO
M
P1[4]
Optional External Clock Input (EXTCLK). 53 IO
M
P2[4]
External Analog Ground (AGND) input.
35
IO
M
P1[6]
54 IO
M
P2[6]
External Voltage Reference (VREF) input.
36
IO
M
P5[0]
55 IO
I,M
P0[0]
Analog column mux input.
37
IO
M
P5[2]
56 IO
I,M
P0[2]
Analog column mux input and column output.
38
IO
M
P5[4]
57 IO
I,M
P0[4]
Analog column mux input and column output.
39
IO
M
P5[6]
58 IO
I,M
P0[6]
Analog column mux input.
40
IO
M
P3[0]
59 Power
Vdd
Supply voltage.
41
IO
M
P3[2]
60 Power
Vss
Ground connection.
42
IO
M
P3[4]
61 IO
I,M
P0[7]
Analog column mux input, integration input #1
43
IO
M
P3[6]
62 IO
IO,M
P0[5]
Analog column mux input and column output,
integration input #2.
44
HCLK
OCD high-speed clock output.
63 IO
IO,M
P0[3]
Analog column mux input and column output.
45
CCLK
OCD CPU clock output.
64 IO
I,M
P0[1]
Analog column mux input.
46
Input
XRES
Active high pin reset with internal pull
down.
65 IO
M
P2[7]
47
IO
M
P4[0]
66 IO
M
P2[5]
48
IO
M
P4[2]
67 IO
I,M
P2[3]
Direct switched capacitor block input.
49
IO
M
P4[4]
68 IO
I,M
P2[1]
Direct switched capacitor block input.
LEGEND
A = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
QFN
(Top View)
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