2 / 9 page  PRELIMINARY CY2DP818-2 Document #: 38-07588 Rev. *A Page 2 of 9 Pin Configuration Figure 1. Pin Diagram - 38-Pin TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND VDD Q1A Q1B Q2A Q2B Q3A Q3B Q4B Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND Q4A GND VDD GND GND VDD InConfig INPUT A INPUT B GND GND VDD EN1 EN2 EN3 EN5 EN6 EN7 VDD EN4 Pin Description Pin Number Pin Name Pin Standard Interface Description 1, 9,12,18,19,20,38 GND POWER Ground. 2,8,13,29,17 VDD POWER Power supply. 3,4,5,6,14,15,16 EN(1:7) LVTTL/LVCMOS The respective outputs are enabled when these pins are pulled high. Outputs are disabled when connected to GND. EN7 controls both Q7(A,B) and Q8(A,B) 10,11 Input A, Input B Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) LVPECL Differential outputs. 7 InConfig LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1) See Input Receiver Configuration for Differential or LVTTL/LVCMOS table, Figure 6 and Figure 7 for additional information [+] Feedback [+] Feedback [+] Feedback |
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