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MPC5533MVZ66 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

Part # MPC5533MVZ66
Description  Microcontroller Data Sheet
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5533MVZ66 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc

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MPC5533 Microcontroller Data Sheet, Rev. 0.0
Overview
Freescale Semiconductor
2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The host processor core of the MPC5533 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The MPC5533 has a single-level memory hierarchy consisting of 48-kilobytes (KB) on-chip SRAM and
768 KB of internal flash memory. Both the SRAM and the flash memory can hold instructions and data.
The complex input/output timer functions of the MPC5533 are performed by an enhanced time processor
unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is
programmed using a high-level programming language.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and an enhanced serial
communications interface (eSCI).
The MCU has an on-chip enhanced queued analog-to-digital converter (eQADC) with a 5 V conversion
range. The 324 package has 40-channels; the 208 package has 34 channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. Interrupts and reset control are
also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing of eQADC
trigger sources and external interrupt signal multiplexing.


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