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TPS650250RHBR Datasheet(PDF) 8 Page - Texas Instruments

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Part # TPS650250RHBR
Description  Power Management IC for Li-Ion Powered Systems
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS650250RHBR Datasheet(HTML) 8 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS
TPS650250
SLVS843 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 Low Dropout Regulators
I(q)
Operating quiescent current
Current per LDO into VINLDO
16
30
µA
I(SD)
Shutdown current
Total current into VINLDO, VLDO = 0V
0.6
2
µA
VI
Input voltage range for LDO1, LDO2
1.5
6.5
V
VO
LDO1 output voltage range
1
3.3
V
LDO2 output voltage range
1
3.3
V
VFB
LDO1 and LDO2 feedback voltage
See (1)
1.0
V
IO
Maximum output current for LDO1, LDO2
VI = 1.8V, VO = 1.3V
200
mA
IO
Maximum output current for LDO1, LDO2
VI = 1.5V; VO = 1.3V
120
mA
ISC
LDO1 and LDO2 short circuit current limit
VLDO1 = GND, VLDO2 = GND
400
mA
Minimum voltage drop at LDO1, LDO2
IO = 50mA, VINLDO = 1.8V
120
mV
Minimum voltage drop at LDO1, LDO2
IO = 50mA, VINLDO = 1.5V
65
150
mV
Minimum voltage drop at LDO1, LDO2
IO = 200mA, VINLDO = 1.8V
300
mV
Output voltage accuracy for LDO1, LDO2
IO = 10mA
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1,2 = VLDO1,2 + 0.5V (min. 2.5V) to 6.5V,
–1%
1%
IO = 10mA
Load regulation for LDO1, LDO2
IO = 0mA to 200mA
–1%
1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
10
µs
Vdd_alive Low Dropout Regulator
Vdd_alive
Vdd_alive LDO output voltage, TPS6502500 to
IO = 0mA
1.0
V
TPS6502504
IO
Output current for Vdd_alive
30
mA
I(SC)
Vdd_alive short circuit current limit
Vdd_alive = GND
100
mA
Output voltage accuracy for Vdd_alive
IO = 0mA
–1%
1 %
Line regulation for Vdd_alive
VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0mA
–1%
1 %
Regulation time for Vdd_alive
Load change from 10% to 90%
10
µs
AnaLogic Signals DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High level input voltage
1.3
VCC
V
VIL
Low level input voltage
0
0.1
V
IH
Input bias current
0.001
0.05
µA
THERMAL SHUTDOWN
TSD
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shudown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDER VOLTAGE LOCK OUT
UVLO
Internal UVLO
VCC falling
–3%
2.35
3%
V
VUVLO_HYST
internal UVLO comparator hysteresis
120
mV
VOLTAGE DETECTOR COMPARATOR
PWRFAIL_SNS
Comparator threshold
Falling threshold
–2%
1.0
2%
V
Hysteresis
40
50
60
mV
Propagation delay
25mV overdrive
10
µs
VOL
Power fail output low voltage
IOL = 5 mA
0.3
V
(1)
If the feedback voltage is forced higher than above 1.2V, a leakage current into the feedback pin may occur.
8
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS650250


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