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DS4266D+ Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS4266D+ Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 6 page DDR Clock Oscillator _______________________________________________________________________________________ 5 Detailed Description The DS4266 consists of a fundamental-mode crystal and synthesizer IC packaged in a 5mm x 3.2mm x 1.49mm, 10-pin LCCC ceramic package. The device produces a frequency output of 266.00MHz. Two differ- ential output types are available: LVDS and LVPECL. The device output can be enabled or disabled through the OE signal input. When the OE signal is low, LVPECL outputs go to the PECL_BAS level of VCC - 2.9V, while the LVDS outputs are a logical 1. See Figures 2 and 3 for LVDS and LVPECL output timing diagrams. Additional Information For more available frequencies in the DS4-XO family, refer to the DS4125 data sheet at www.maxim- ic.com/DS4125. X1 X2 THREE- STATE PHASE DET FILTER LC-VCO /n OUTSELN /m OUTDRV VCC GND OE OUTP OUTN DS4266 Figure 1. Functional Diagram OE OUTP tP1A tPA1 0.7 x VCC 0.3 x VCC OUTN Figure 2. LVDS Output Timing Diagram When OE Is Enabled and Disabled OE OUTP PECL_BIAS PECL_BIAS PECL_BIAS PECL_BIAS OUTN 0.7 x VCC 0.3 x VCC tPAZ tPZA Figure 3. LVPECL Output Timing Diagram When OE Is Enabled and Disabled |
Similar Part No. - DS4266D+ |
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Similar Description - DS4266D+ |
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