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TPS71812-33DRVTG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS71812-33DRVTG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page ABSOLUTE MAXIMUM RATINGS (1) DISSIPATION RATINGS TPS718xx TPS719xx SBVS088C – FEBRUARY 2007 – REVISED MAY 2008..................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT (2) (3) TPS718xx-yywwwz A denotes device with rotated pin 1 orientation of wafer-chipscale package. TPS718Axx-yywwwz XX is nominal output voltage for LDO1 (for example, 28 = 2.8V). TPS719xx-yywwwz YY is nominal output voltage for LDO2. TPS719Axx-yywwwz WWW is package designator. Z is tape and reel quantity (R = 3000, T = 250). Examples: TPS71918–285DRVR XX = 18 = 1.8V, YYY = 285 = 2.85V TPS719185-33DRVR XXX = 185 = 1.85V, YY = 33 = 3.3V DRV = 2mm x 2mm SON package Z = R = 3000 piece reel (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Both outputs are programmable from 0.9V to 3.6V in 50mV increments. (3) Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Over operating temperature range (unless otherwise noted). All voltages are with respect to GND. PARAMETER TPS718xx, TPS719xx UNIT Input voltage range, VIN –0.3 to +7.0 V Enable voltage range, VEN1 and VEN2 –0.3 to VIN + 0.3V V Output voltage range, VOUT –0.3 to +7.0 V Peak output current Internally limited Output short-circuit duration Indefinite Junction temperature range, TJ –55 to +150 °C Storage temperature range , TSTG –55 to +150 °C Total continuous power dissipation, PDISS See Dissipation Ratings Table ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DERATING FACTOR BOARD PACKAGE RθJC RθJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C High-K(1) DRV 20 °C/W 95 °C/W 10.53mW/ °C 1053mW 579mW 421mW High-K(1) YZC 27 °C/W 190 °C/W 5.3mW/ °C 530mW 295mW 215mW (1) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS718xx TPS719xx |
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