ADS6148IRGZR datasheet(6/70 Pages) TI

Part #	ADS6148IRGZR

Description	14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

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Manufacturer	TI [Texas Instruments]

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ELECTRICAL CHARACTERISTICS – ADS614X and ADS612X

ADS6149/ADS6129

ADS6148/ADS6128

SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com

Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal

reference mode unless otherwise noted.

Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V

ADS6149/ADS6129

ADS6148/ADS6128

250 MSPS

210 MSPS

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

ANALOG INPUT

Differential input voltage range

2

VPP

Differential input resistance (at dc), See Figure 97

>1

M

Ω

Differential input capacitance, See Figure 98

3.5

pF

Analog Input Bandwidth

700

MHz

Analog Input common mode current (per input pin)

2

µA/MSPS

VCM Common mode output voltage

1.5

V

VCM output current capability

±4

mA

DC ACCURACY

Offset error

–15

±2

15

–15

±2

15

mV

Temperature coefficient of offset error

0.005

mV/°C

Variation of offset error with supply

0.3

mV/V

EGREF

Gain error due to internal reference inaccuracy alone

–1.25

±0.2

1.25

–1.25

±0.2

1.25

%FS

EGCHAN

Gain error of channel alone

0.2

%FS

Temperature coefficient of EGCHAN

.001

Δ%/°C

POWER SUPPLY

IAVDD

Analog supply current

170

155

mA

Output buffer supply current, LVDS interface with 100

Ω external

70

65

mA

termination

IDRVDD

Output buffer supply current, CMOS interface Fin = 3 MHz(1),

56

48

mA

10-pF external load capacitance

Analog power

561

630

510

570

mW

Digital power LVDS interface

126

160

118

153

mW

Digital power CMOS interface, Fin = 3 MHz(2), 10-pF external

101

87

mW

load capacitance

Global power down

20

50

20

50

mW

Standby

120

mW

(1)

In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the

supply voltage (see Figure 91 and CMOS interface power dissipation in application section).

(2)

The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the

maximum recommended load capacitance on each digital output line is 10 pF.

6

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