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AD5762RCSUZ-REEL7 Datasheet(PDF) 11 Page - Analog Devices |
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AD5762RCSUZ-REEL7 Datasheet(HTML) 11 Page - Analog Devices |
11 / 32 page AD5762R Rev. 0 | Page 11 of 32 NC = NO CONNECT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SYNC SCLK SDIN SDO CLR LDAC D1 D0 NC NC VOUTA AGNDA AGNDB VOUTB NC NC 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 PIN 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 AD5762R TOP VIEW (Not to Scale) Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 2 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. 3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 4 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. 5 CLR Negative Edge Triggered Input.1 Asserting this pin sets the DAC registers to 0x0000. 6 LDAC Load DAC. This logic input is used to update the DAC registers and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 7, 8 D0, D1 Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND. 9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. 10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. 11 DGND Digital Ground Pin. 12 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V. 13, 31 AVDD Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. 14 PGND Ground Reference Point for Analog Circuitry. 15, 30 AVSS Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V. 16 ISCC This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for more information. 17 NC Do not connect to this pin. 18 NC Do not connect to this pin. 19 VOUTB Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 20 AGNDB Ground Reference Pin for DAC B Output Amplifier. 21 AGNDA Ground Reference Pin for DAC A Output Amplifier. |
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