New Product

TPSMP6.8 thru TPSMP43A

Vishay General Semiconductor

www.vishay.com

For technical questions within your region, please contact one of the following:

PDD-Americas@vishay.com, PDD-Asia@vishay.com, PDD-Europe@vishay.com

Document Number: 88471

Revision: 21-Oct-08

4

PACKAGE OUTLINE DIMENSIONS in inches (millimeters)

Figure 5. Maximum Peak Forward Surge Current

40

35

30

25

20

15

10

5

0

1

10

100

Number of Cycles at 50 Hz

Figure 6. Steady State Power Derating Curve

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0

25

50

75

100

125

150

175

200

T

FR-4 PCB, on Vishay minimum

recommended Pad Layout

0.000 (0.00)

0.012 (0.30)

0.013 (0.35)

0.004 (0.10)

0.018 (0.45)

0.006 (0.15)

0.045 (1.15)

0.033 (0.85)

0.036 (0.91)

0.024 (0.61)

0.016 (0.40)

0.032 (0.80)

0.053 (1.35)

0.041 (1.05)

0.012 (0.30) REF.

0.105

(2.67)

0.025

(0.635)

0.100

(2.54)

0.030

(0.762)

0.050

(1.27)

Cathode Band

0.142 (3.61)

0.126 (3.19)

0.158 (4.00)

0.146 (3.70)

0.086 (2.18)

0.074 (1.88)

0.087 (2.20)

0.103 (2.60)

DO-220AA (SMP)