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TDA9112 Datasheet(PDF) 30 Page - STMicroelectronics |
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TDA9112 Datasheet(HTML) 30 Page - STMicroelectronics |
30 / 51 page TDA9112 30/51 Figure 6. Horizontal oscillator (VCO) schematic diagram 9.3.3 - Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an “output” to PLL1 and “input” to PLL2. It delivers a linear sawtooth. Figure 6 ex- plains its principle of operation. The linears are ob- tained by charging and discharging an external ca- pacitor on pin CO, with currents proportional to the current forced through an external resistor on pin RO, which itself depends on the input tuning volt- age VHO (filtered charge pump output). The rising and falling linears are limited by VHOThrLo and VHOThrHi thresholds filtered through HOscF pin. At no signal condition, the VHO tuning voltage is clamped to its minimum (see chapter ELECTRI- CAL PARAMETERS AND OPERATING CONDI- TIONS, part horizontal section), which corre- sponds to the free-running VCO frequency fHO(0). Refer to Note 1 for formula to calculate this fre- quency using external components values. The ra- tio between the frequency corresponding to maxi- mum VHO and the one corresponding to minimum VHO (free-running frequency) is about 4.5. This range can easily be increased in the application. The PLL1 can only lock to input frequencies falling inside these two limits. 9.3.4 - PLL2 The goal of the PLL2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a cer- tain threshold of the VCO sawtooth. This internal threshold is affected by geometry phase correc- tions, like e.g., parallelogram. The PLL2 is much faster than PLL1 to be able to follow the dynamism of phase modulation. The PLL2 control current (see Figure 7) is significantly increased during dis- charge of vertical oscillator (during vertical retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. The PLL2 control current is integrated on the external filter on pin HPLL2C to obtain smoothed voltage, used, in comparison with VCO ramp, as a threshold for H-drive rising edge gener- ation. As both leading and trailing edges of the H-drive signal in the Figure 7 must fall inside the rising part of the VCO ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of H-drive signal with maximum duty cycle. Yet, the constraints thereof must be taken into account while consider- ing the application frequency range and H-flyback duration. The Figure 7 also shows regions for ris- ing and falling edges of the H-drive signal on HOut pin. As it is forced high during the H-flyback pulse and low during the VCO discharge period, no edge during these two events takes effect. The flyback input configuration is in Figure 8. 9.3.5 - Dynamic PLL2 phase control The dynamic phase control of PLL2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. It is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchroniza- tion). Inside the device, the threshold VS(0) is com- pared with the VCO ramp, the PLL2 locking the middle of H-flyback to the moment of their match. The dynamic phase is obtained by modulation of the threshold by correction waveforms. Refer to Figure 12 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction waveforms have no effect in vertical middle of the screen (for mid- dle vertical position). As they are summed, their ef- fect on the phase tends to reach maximum span at top and bottom of the picture. As all the compo- nents of the resulting correction waveform (linear for parallelogram correction, parabola of 2nd order for Pin cushion asymmetry correction and half-pa- RS Flip-Flop CO VHOThrHi 4I0 I0 2 HPLL1F I0 RO 9 + - (PLL1 filter) 6 HOscF + - + - 4 VHOThrLo VHOThrLo VHOThrHi 8 from charge pump VHO VCO discharge control |
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