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TDA9109SN Datasheet(PDF) 16 Page - STMicroelectronics

Part No. TDA9109SN
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com

TDA9109SN Datasheet(HTML) 16 Page - STMicroelectronics

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I.1 - Power Supply
The typical values of the power supply voltages
VCC and VDD are 12V and 5V respectively. Opti-
mum operation is obtained for VCC between 10.8
and 13.2V and VDD between 4.5 and 5.5V.
In orderto avoiderraticoperationof thecircuit during
the transient phase of VCC and VDD switching on, or
off, the value of VCC and VDD are monitored : if VCC
is less than 7.5V typ. or if VDD is less than 4.0V typ.,
the outputs of the circuit are inhibited.
Similarly, beforeVDD reaches4V, all the I
2C register
are reset to their default value.
In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value : 8V). Two of these voltage
references are externally accessible, one for the
vertical and one for the horizontal part. They can be
used to bias external circuitry (if ILOAD is less than
5mA). It is necessary to filter the voltagereferences
by externalcapacitorsconnectedto ground,in order
to minimize the noise and consequently the ”jitter”
on vertical and horizontal output signals.
I.2 - I
2C Control
TDA9109/SN belongs to the I
2C controlled device
family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I
2C Interface.
The I
2C bus is a serial bus with a clock and a data
input. The general function and the bus protocolare
specified in the Philips-bus data sheets.
The interface (Data and Clock)is a comparatorwith
hysteresis ; the thresholds(less then 2.2V on rising
edge, more than 0.8V on falling edge with 5V
supply) are TTL-compatible. Spikes of up to 50ns
are filtered by an integrator and the maximum clock
speed is limited to 400kHz.
The data line (SDA) can be used bidirectionally.
In read-mode the IC sends reply information
(1 byte) to the micro-processor.
The bus protocol prescribes a full-byte transmis-
sion in all cases. The first byte after the start
condition is used to transmit the IC-address
(hexa 8C for write, 8D for read).
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controls to affect)and the thirdbyte the correspond-
ing data byte. It is possible to send more than one
data byte to the IC. If after the third byte no stop or
start condition is detected, the circuit increments
automatically by one the momentary subaddressin
the subaddress counter (auto-increment mode).
So it is possible to transmit immediately the follow-
ing data bytes without sending the IC address or
subaddress.This can be useful to reinitialize all the
controls very quickly (flash manner). This proce-
dure can be finished by a stop condition.
The circuit has 14 adjustment capabilities : 1 for the
horizontal part, 4 for the vertical, 2 for the E/W
correction, 2 for the dynamic horizontal phase con-
trol,1 for the Moiré option, 3 for the horizontal and
the vertical dynamic focus and 1 for the B+ refer-
ence adjustment.
17 bits are also dedicated to several controls
(ON/OFF, Horizontal Forced Frequency, Sync Pri-
ority, Detection Refresh and XRAY reset).
I.4 - Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status and,
the horizontal and vertical polarity detection. It also
contains the sync detection status which is used by
the MCU to assign the sync priority.
A stop conditionalways stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).
See I
2C subaddressand control tables.
I.5 - Sync Processor
T h e i nt ernal s ync p rocess o r a ll ows t he
TDA9109/SN to accept :
- separated horizontal & vertical TTL-compatible
sync signal,
- composite horizontal & vertical TTL-compatible
sync signal.

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