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TDA9105A Datasheet(PDF) 15 Page - STMicroelectronics |
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TDA9105A Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 31 page  OPERATING DESCRIPTION (continued) LOCKDET 2 H-LOCKOUT 13 H-LOCKCAP COMP1 INPUT INTERFACE 17 H-SYNC High CHARGE PUMP Low PLL INHIBITION VCO 14 PLL1INHIB 12 11 10 PLL1F R0 C0 PHASE ADJUST E2 15 H-POS 3.2V OSC Figure 11 : Principle Diagram The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A “CRC” filter is generally used (see Figure 9). PLL1 is inhibited by applying a high level on Pin 14 (PLLinhib)which is a TTL compatibleinput. The inhibi- tion results from the opening of a switch located be- tween the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and dis- charge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V (see Figure 10). The control voltage of the VCO is typically com- prised between 1.6V and 6V (see Figure 10). The theoreticalfrequencyrange of thisVCO is in the ratio 1 → 3.75, but due to spread and thermal drift of external componentsand the circuit itself, the effec- 12 PLL1F Figure 12 tive frequency range has to be smaller (e.g. 30kHz → 85kHz).In the absenceof synchronisationsignal the control voltageis equal to 1.6V typ. and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhas to be alwayshigherthan the free frequencyand a margin has to be taken. As an example for a synchro range from 30kHz to 85kHz, the suggested free frequency is 27kHz. 11 12 Loop Filter R0 1.6V 6.4V 10 C0 6.4V 1.6V 0 0.75T T RS FLIP FLOP (1.6V < V < 6V) 12 I0 I0 2 4I0 2 Figure 13 : Details of VCO TDA9105A 15/31 |
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