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TDA9105 Datasheet(PDF) 22 Page - STMicroelectronics

Part No. TDA9105
Description  DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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TDA9105 Datasheet(HTML) 22 Page - STMicroelectronics

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OPERATING DESCRIPTION (continued)
VERTICAL PART (continued)
Function
When the synchronisation pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
Typical free running frequency can be calculated
by :
f0
(Hz)= 1.5 ⋅ 10−5
1
COSC
(nF)
A negative or positive TTL level pulse applied on
Pin 34 (VSYNC) can synchronise the ramp in the
frequency range [fmin, fmax]. This frequency range
depends on the external capacitor connected on
Pin 27. A capacitor in the range [150nF, 220nF] is
recommanded for application in the following
range : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25
°C
and without any correction (S correction or C cor-
rection), can be calculated by :
fmax = 2.5
⋅ f0 and fmin = 0.33 ⋅ f0
If S or C corrections are applied, these values are
slighty affected.
If an external synchronisation pulse is applied, the
internal oscillator is automaticaly caught but the
amplitude is no more constant. An internal correc-
tion is activated to adjust it in less than half a
second: the highest voltage of the ramp on Pin 27
is sampled on the sampling capacitor connected on
Pin 25 (VAGCCAP) at each clock pulse and a
transconductance amplifier generates the charge
current of the capacitor. The ramp amplitude be-
comes again constant.
It is recommanded to use a AGC capacitor with low
leakage current. A value lower than 100nA is man-
datory.
Pin 36, Vfly is the vertical flyback input used to
generate the composite blanking signal. If Vfly is
not used, (VREF - 0.5), at minimum, must be con-
nected to this input.
DC Control Adjustments
Then, S and C correction shapes can be added to
this ramp. This frequency independent S and C
corrections are generated internally; their ampli-
tude are DC adjustable on Pin 28 (VSAMP) and
Pin 29 (COR-C).
S correction is non effective for VSAMP lower than
VREF/4 and maximum for VSAMP = 3/4
⋅ VREF.
C correction is non effective for COR-C grounded
and maximum for :
COR-C = VREF/4 or COR-C = 3/4
⋅ VREF.
Endly, the amplitude of this S and C corrected ramp
can be adjusted by the voltage applied on Pin 31
(VAMP). The adjusted ramp is available on Pin 30
(VOUT) to drive an external power stage. The gain
of this stage is typically
±30% when voltage applied
on Pin 31 is in the range VREF/4 to 3/4
⋅ VREF.The
DC value of this ramp is kept constant in the
frequency range , for any correction applied on it.
Its typical value is : VDCOUT =VMID = 7/16
⋅ VREF.
A DC voltage is available on Pin 32 (VDCOUT). It is
driven by the voltage applied on Pin 33 (VPOS)
For a voltage control range between VREF/4 and
3/4
⋅ VREF, the voltage available on Pin 32 is :
VDCOUT = 7/16
⋅ VREF ± 300mV.
So, the VDCOUT voltage is correlated with DC value
of VOUT. It increases the accuracy when tempera-
ture varies.
Basic Equations
In first approximation, the amplitude of the ramp on
Pin 30 (VOUT)is :
VOUT -VMID =(VCAP -VMID) [1 + 0.16
⋅ (VAMP -VREF/2)]
with VMID = 7/16
⋅ VREF ; typically 3.5V
VMID is the middle value of the ramp on Pin 27
VCAP =V27 , ramp with fixed amplitude.
On Pin 32 (VDCOUT), the voltage (in volts) is calcu-
lated by : VDCOUT =VMID + 0.16
⋅ (VPOS -VREF/2).
VPOS is the voltage applied on Pin 33.
The current available on Pin 27
(when VSAMP =VREF/4) is :
IOSC = 3/8
⋅ VREF ⋅ COSC ⋅ f
COSC : capacitor connected on Pin 27
f synchronisation frequency
The recommanded capacitor value on Pin 25
(VAGC) is 470nF. Its ensures a good stability of the
internal closed loop.
TDA9105
22/32


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