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TDA9105 Datasheet(PDF) 14 Page - STMicroelectronics

Part No. TDA9105
Description  DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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TDA9105 Datasheet(HTML) 14 Page - STMicroelectronics

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OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical value of the power supply voltage VCC
is 12V. Perfect operation is obtained if VCC is main-
tained in the limits : 10.8V
→ 13.2V.
In order to avoid erratic operation of the circuit
during the transient phase of VCC switching on, or
switching off, the value of VCC is monitored and the
outputs of the circuit are inhibited if VCC < 7.6 typi-
cally.
In order to have a very good power supply rejection,
the circuit is internally powered by several internal
voltage references (The unique typical value of
which is 8V). Two of these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
applied on the concerned pins by the way of poten-
tiometers or digital to analog converters (DAC’s).
Furthermore it is necessary to filter the a.m. voltage
references by the use of external capacitor con-
nected to ground, in order to minimize the noise
and consequently the ”jitter” on vertical and hori-
zontal output signals.
DC Control Adjustments
The circuit has 10 adjustment capabilities : 2 for the
horizontal part, 2 for the E/W correction, 4 for the
vertical part, 2 for the Dynamic Horizontal phase
control.
The corresponding inputs of the circuit has to be
driven with a DC voltage typically comprised be-
tween 2 and 6V for a value of the internal voltage
reference of 8V.
PWM
DAC
Output
DC Control
Voltage
V
REF
Figure 5 :
Example of Practical DC Control
Voltage Generation
Figure 7
H-SYNC
1.6V
Figure 6 : Input Structure
In order to have a good tracking with the voltage
reference value, it’s better to maintain the control
voltages between VREF/4 and 3/4
⋅ VREF.
The input current of the DC control inputs is typi-
cally very low (about a few
µA). Depending on the
internal structure of the inputs, it can be positive or
negative (sink or source).
HORIZONTAL PART
Input section
The horizontal input is designed to be sensitive to
TTL signals typically comprised between 0 and 5V.
The typical threshold of this input is 1.6V. This input
stage uses an NPN differential stage and the input
current is very low.
Concerning the duty cycle of the input signal, the
following signals may be applied to the circuit.
Using internal integration, both signals are recog-
nized on condition that Z/T
≤ 25%. Synchronisation
occurs on the leading edge of the internal sync
signal. The minimum value of Z is 0.7
µs.
PLL1
The PLL1 is composed of a phase comparator, an
external filter and a Voltage Controlled Oscillator
(VCO).
The phase comparator is a ”phase frequency” type,
designed in CMOS technology. This kind of phase
detector avoids locking on false frequencies. It is
followed by a ”charge pump”, composed of 2 cur-
rent sources sink and source (I = 1mA typ.)
TDA9105
14/32


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