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M5M5256DFP Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # M5M5256DFP
Description  262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M5M5256DFP Datasheet(HTML) 6 Page - Renesas Technology Corp

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RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
6
Write cycle ( /S control mode)
tsu (S)
trec (W)
th (D)
tCW
(Note 5)
(Note 3)
(Note 3)
tsu (A)
(Note 4)
tsu (D)
DATA IN
STABLE
DQ1~8
/S
/W
A0~14
Note 3 : Hatching indicates the state is "don't care".
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inv erted phase signal externally when DQ pin is output mode.
4 : Writing is executed in ov erlap of /S and /W low.
7 : ten, tdis are periodically sampled and are not 100% tested.
(4) MEASUREMENT CONDITIONS
Input pulse level .............. VIH=2.4V,VIL=0.6V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.2, CL=100pF
CL=5pF (for ten,tdis)
T ransition is measured ±500mV from steady
state voltage. (for ten,tdis)
Vcc
DQ
CL
Fig.2 Output load
1.8k
990
(Including
scope and JIG)
Limits1:Vcc=3.3±0.3V
Input pulse level .............. VIH=2.4V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.1, CL=30pF
CL=5pF (for ten,tdis)
T ransition is measured ±500mV from steady
state voltage. (for ten,tdis)
Limits2:Vcc=5.0±0.5V
DQ
CL
Fig.1 Output load
(Including
scope and JIG)


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