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APD-256G064-1 Datasheet(PDF) 2 Page - Vishay Siliconix

Part No. APD-256G064-1
Description  Plasma Panel Display Module 256 x 64 Graphics Display with Drive Electronics, TTL Level Data Interfacer and Integrated DC Converter
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
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APD-256G064-1 Datasheet(HTML) 2 Page - Vishay Siliconix

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APD-256G064-1
Vishay Dale
Document Number: 37020
Revision 05-Dec-00
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK - This signal enters the SERIAL DATA on each
low to high transition. A total of 256 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA - This signal presents the pixel data in
positive logic format. A logic one represents a lit pixel and a
logic zero represents an extinguished pixel. Data is entered
from right to left. The first pixel data entered will represent
the leftmost pixel in the row.
COLUMN LATCH - This signal latches the pixel data into the
driver outputs. When the COLUMN LATCH signal goes to
logic one the data entered previously will fall through to the
driver outputs. When the signal returns to a logic zero, the
data is latched and the shift register is now ready to accept
the next row of data. Must be held low while entering new
SERIAL DATA.
DISPLAY ENABLE - This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To
avoid display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10
µS min.
ROW DATA - This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK - This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-256G064-1 has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins scan-
ning).
ORDERING INFORMATION
Display Module with Drivers, TTL Interface and On Board Converter............................................................... ................ APD-256G064-1
Data Connector Kit...................................................................................................................................................... ................ 280105-05
Power Connector Kit................................................................................................................................................... ................ 280108-13
Video Controller (+5V) Parallel and Serial Interface...................................................................................................... ................. PDS-500
Video Controller (+12V) Parallel and Serial Interface................................................................................................. ................ PDS-500-1
PIN DESCRIPTION
P3, POWER CONNECTOR
PIN
1
2
3
4
5
DESCRIPTION
Vbb
DC Converter Supply
Logic Supply
Used to key connector
Vbb and Vcc
SIGNAL
GND
VDC
Vcc
KEY
GND
AMP #640445-5 or equivalent.
(Mates with AMP 640428-5, MOLEX 09-05-3051 or equivalent.)
P2, DATA CONNECTOR
AMP #103309-2 or equivalent.
(Mates with AMP 746195-2, MOLEX 39-27-1146 or equivalent.)
DESCRIPTION
DISPLAY ENABLE
ROW DATA
ROW CLOCK
COLUMN LATCH
DOT CLOCK
SERIAL DATA
No connect
PIN
1
3
5
7
9
11
13
PIN
2
4
6
8
10
12
14
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
Display Enable
LOGIC AND DATA TIMING
Serial Data
Dot Clock
t7
1st Bit of Row Will Appear in Leftmost Column
0
1
2
254 255
t6
t5
Positive Edge x 256
Row Data
Row Clock
Display Enable
0
t2
t1
t4
1
63
62
2
1
0
63
62
2
1
0
t3
01
Row Clock
Column Latch
PARAMETER
t1
t2
t3
t4
t5
t6
t7
MINIMUM
100
5
1
25
75
75
TYPICAL
70
MAXIMUM
200
UNITS
nS
uS
uS
Hz
nS
nS
nS


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