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SN74V245-10PAG Datasheet(PDF) 6 Page - Texas Instruments |
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SN74V245-10PAG Datasheet(HTML) 6 Page - Texas Instruments |
6 / 43 page SN74V215, SN74V225, SN74V235, SN74V245 512 × 18, 1024 × 18, 2048 × 18, 4096 × 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) READ ENABLE (REN) When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When REN is high, the output register holds the previous data and no new data is loaded into the output register. Data outputs Q0–Qn maintain the previous data value. In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high, allowing a read to occur. The EF flag is updated on the rising edge of RCLK. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid low-to-high transition of RCLK + tSKEW after the first write. REN need not be asserted low. To access all other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read operations. REN is ignored when the FIFO is empty. OUTPUT ENABLE (OE) When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output data bus is in the high-impedance state. LOAD (LD) The SN74V215, SN74V225, SN74V235, and SN74V245 devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. When LD is low and WEN is low, data on the inputs D0–D11 is written into the empty offset register on the first low-to-high transition of the write clock (WCLK). When LD and WEN are held low, data is written into the full offset register on the second low-to-high transition of WCLK (see Tables 1 and 2). The third transition of WCLK again writes to the empty-offset register. However, writing to all offset registers need not occur at one time. One or two offset registers can be written and then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low, the next offset register in sequence is written. Table 1. Writing to Offset Registers LD WEN WCLK SELECTION† L L ↑ Writing to offset registers: Empty offset Full offset L H ↑ No operation H L ↑ Write into FIFO H H ↑ No operation † The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the low-to-high transition of RCLK. |
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