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APD-128G064D Datasheet(PDF) 2 Page - Vishay Siliconix

Part No. APD-128G064D
Description  Plasma Panel Display Modules 128 x 64 Graphics Display with Video Interface, DC Converter and Drive Circuitry
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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APD-128G064D Datasheet(HTML) 2 Page - Vishay Siliconix

   
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APD-128G064D
Vishay Dale
Document Number: 37055
Revision 05-Dec-00
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK: This signal enters the SERIAL DATA on each
low to high transition. A total of 128 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA: This signal presents the pixel data in
positive logic format. A logic one represents a lit pixel and a
logic zero represents an extinguished pixel. Data is entered
from right to left. The first pixel data entered will represent
the leftmost pixel in the row.
COLUMN LATCH: This signal latches the pixel data into the
driver outputs. When the COLUMN LATCH signal goes to
logic one the data entered previously will fall through to the
driver outputs. When the signal returns to a logic zero, the
data is latched and the shift register is now ready to accept
the next row of data. Must be held low while entering new
SERIAL DATA.
DISPLAY ENABLE: This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To
avoid display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10
µS minutes.
ROW DATA: This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK: This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-128G064D has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins scan-
ning).
This information is subject to change without notice.
SIGNAL DESCRIPTION
PIN
FUNCTION
DESCRIPTION
1
DEm
Display enable signal
3
Rdata
Row driver data input
5
Rclk
Row clock
7
latch
Column latch
9
Dot CLK
Dot clock
11
Sdata
Serial column data
*
GND
Common Ground
POWER SUPPLY CONNECTION
CONNECTOR
PIN
SIGNAL
J1
1
+ 12 VDC
2
GROUND
3
GROUND
4
N/C
*NOTE: The maximum VDC draw denotes a power up condition
when the DC converter starts. Typical duration is 15-30 mS.
VDC
+ 12 V
± 0.6 V
1.5 A Max.*, 0.4 A Typ.
POWER SUPPLY: (Recommended)
Display
Enable
LOGIC AND DATA TIMING
Serial Data
Dot Clock
t7
1st Bit of Row Will Appear in Leftmost Column
01
2
126
127
t6
t5
Positive Edge x 192
Row Data
Row Clock
Display
Enable
0
t2
t1
t4
1
63
62
2
1
0
63
62
2
1
00
1
Row Clock
Column
Latch
t3
PARAMETER
MINIMUM
TYPICAL
MAXIMUM
UNITS
t1
130
112
nS
t2
75
1000
uS
t3
16.6
14.3
uS
t4
5
20
200
Hz
t5
25
——
nS
t6
75
——
nS
t7
75
——
nS
ORDERING INFORMATION
DESCRIPTION
PART NUMBER
Display Unit ........................................................ APD-128G064D
Non-Glare Filter (Amber CP) ...................................... 280109-19
Video Controller (+ 5V) .................................................. PDS-500
Video Controller (+ 12V) ............................................. PDS-500-1
APPLICABLE MATING
CONNECTORS
MANUFACTURER PART NUMBER
TO POWER INPUT (P1) ........... MOLEX .................. 09-50-3081
MOLEX .................. 09-06-5087
AMP ....................... 640428-8
METHODE .................. 3300-108
TO LOGIC INPUT (P2) ............. MOLEX .................. 39-27-1146
ROBINSON NUGENT....IDS-C14PK-TC
AMP ...... 746195-2, 746582-2
3M .... 3314-5002, 3314-5202
Vishay Dale Power
Connector Kit 280108-05
Vishay Dale Data
Connector Kit
280108-05


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