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M38049FFKP Datasheet(PDF) 77 Page - Renesas Technology Corp |
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M38049FFKP Datasheet(HTML) 77 Page - Renesas Technology Corp |
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77 / 387 page  1-59 REJ09B0212-0100Z Rev.1.00 Jan 14, 2005 3804 Group (Spec.H) HARDWARE FUNCTIONAL DESCRIPTION XIN Data bus XCIN “10” “00” “01” Main clock division ratio selection bits (Note) “0” “1” 1/16 Watchdog timer H count source selection bit Reset circuit STP instruction disable bit Watchdog timer H (8) “FF16” is set when watchdog timer control register is written to. Internal reset RESET Watchdog timer L (8) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. STP instruction “FF16” is set when watchdog timer control register is written to. Reset release time waiting WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to “FF16” and watchdog timer H is set to “FF16” by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write sig- nal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. Fig. 55 Structure of Watchdog timer control register When bit 6 of the watchdog timer control register is kept at “0”, the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP in- struction is disabled by writing “1” to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a “1” is written to this bit, it cannot be programmed to “0” again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 µs Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not un- derflow during this period. Fig. 54 Block diagram of Watchdog timer b7 Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Watchdog timer control register (WDTCON : address 001E16) b0 |
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