Electronic Components Datasheet Search |
|
M38048FFKP Datasheet(PDF) 80 Page - Renesas Technology Corp |
|
M38048FFKP Datasheet(HTML) 80 Page - Renesas Technology Corp |
80 / 387 page 1-62 REJ09B0212-0100Z Rev.1.00 Jan 14, 2005 3804 Group (Spec.H) HARDWARE FUNCTIONAL DESCRIPTION Table 8 Set values of I2C clock control register and SCL frequency Fig. 58 Structure of I2C clock control register SCL frequency (at φ = 4 MHz, unit : kHz) (Note 1) Setting value of CCR4–CCR0 Standard clock mode Setting disabled Setting disabled Setting disabled High-speed clock mode CCR4 0 0 0 0 0 0 0 1 1 1 CCR3 0 0 0 0 0 0 0 1 1 1 CCR2 0 0 0 0 1 1 1 1 1 1 CCR1 0 0 1 1 0 0 1 0 1 1 CCR0 0 1 0 1 0 1 0 1 0 1 Setting disabled Setting disabled Setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (Note 3) 166 – (Note 2) – (Note 2) [I2C Clock Control Register (S2)] 001516 The I2C clock control register (S2: address 001516) is used to set ACK control, SCL mode and SCL frequency. •Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 8. •Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is selected. When the bit is set to “1,” the high-speed clock mode is selected. When connecting the bus of the high-speed mode I2C bus stan- dard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) in the high-speed mode (2 division clock). •Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0,” the SDA is auto- matically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is auto- matically made “H” (ACK is not returned). ✽ACK clock: Clock for acknowledgment •Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. When this bit is set to “0,” the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally. 500/CCR value (Note 3) 1000/CCR value (Note 3) 17.2 16.6 16.1 Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctu- ates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not in- crease because “L” duration is extended instead of “H” duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 001516) b7b0 SCL frequency control bits Refer to Table 8. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock |
Similar Part No. - M38048FFKP |
|
Similar Description - M38048FFKP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |