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ENA1173A Datasheet(PDF) 8 Page - Sanyo Semicon Device |
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ENA1173A Datasheet(HTML) 8 Page - Sanyo Semicon Device |
8 / 11 page LV4912GP No.A1173-8/11 (2) Power Down sequence The OFF Time should secure more than 100msec for reduction of the popping noise. Capacitors for Power supply and pin arrangement 1. Capacitors for power supply The capacitors C2 and C3 for power supply connected between IC pins must be inserted using the shortest lines possible. 2. Pin arrangement of the test pins (pins 15 and 16) The test pins (pins 15 and 16) are used as pins for testing before shipment. These pins are not used normally. Therefore, these pins must be left open if the pin arrangement is not performed. Please make sure to connect these pins to GNDs if the pin arrangement is performed. OFF Time STBY MUTE MUTECAP Output pin Internal power supply 3 2 PRE_GND PRE_VD C3 1 µF 22 17 PWR_GND PWR_VD C2 1 µF |
Similar Part No. - ENA1173A |
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Similar Description - ENA1173A |
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