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LE25FW203A Datasheet(PDF) 5 Page - Sanyo Semicon Device

Part No. LE25FW203A
Description  CMOS IC 2M-bit (256K×8) Serial Flash Memory 30MHz SPI Bus
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Maker  SANYO [Sanyo Semicon Device]
Homepage  http://www.ssdc-jp.com/eng/
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 5 page
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LE25FW203A
No.A1190-5/18
Figure 4 Serial Output Timing
Command Definition
"Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read
Figure 5 shows the read timing waveforms.
There are two read commands, the 4 bus cycle read and 5 bus cycle read. Consisting of the first through fourth bus
cycles, the 4 bus cycle read inputs the 24-bit address following (03h) and the data in the designated address is output
synchronized to SCK. The data is output on the falling clock edge of fourth bus cycle bit 0.
Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output using the falling clock edge of fifth bus cycle bit 0. The only difference
between these two commands is whether the dummy bits in the fifth bus cycle are input.
While SCK is being input, the address is automatically incremented inside the device and the corresponding data is
output in sequence.
If the SCK input is continued after the data up to the highest address (3FFFFh) is output, the internal address returns to
the lowest address (00000h) and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected,
the output pin is in a high-impedance state.
Figure 5: Read
4 Bus Read
tHO
tCHZ
tCLZ
SI
tV
CS
SO
SCK
DATA VALID
N+2
N+1
N
CS
High Impedance
DATA
DATA
DATA
SCK
SO
SI
03h
Add.
Add.
Add.
15
MSB
MSB
MSB
0
1
2
3
4
5678
23
16
24
31
39
47
8CLK
Mode0
Mode3
32
40




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