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LE24LB642M Datasheet(PDF) 6 Page - Sanyo Semicon Device |
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LE24LB642M Datasheet(HTML) 6 Page - Sanyo Semicon Device |
6 / 12 page LE24LB642M No.1201-6/12 4 Acknowledge During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has been received. The acknowledge signal is not sent during an EEPROM internal write operation. 5 Device addressing For the purposes of communication, the master device in the system generates the start condition for the slave device. Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” This device has the upper 3-bit of the Slave Device address as the Slave address (S0, S1, S2), which fixed on the inside. The value of Slave address are S0=0, S1=0, S2=0. When the device code input from SDA and the slave addresses are compared with the product’s device code and slave addresses that were set at the mounting stage and found to match, the product sends the acknowledge signal during the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed immediately after the slave device has been switched, the random read command must be used. 1 0 1 0 S2 S1 S0 R/W Device Code Slave Address MSB LSB Device address word Acknowledge bit output Start condition SCL (EEPROM input) SDA (Master output) SDA (EEPROM output) 1 8 9 tAA tDH |
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