LC07422T

No.A0908-8/10

9. Video driver

Negative power is generated by the charge pump circuit and supplied to the video driver. Therefore, the video

driver operates on the positive and negative power supplies.

The video signals are output with no DC components for the ground reference. As a result, with 75

Ω termination,

there is no need for an output coupling capacitor.

In principle, no V sag is generated.

10. Register settings

This is a 3-line system serial control circuit. The three lines are CS_X (Chip Select/low active), SCLK (Serial Clock)

and SDin (Serial Data). Data can only be written into the register: The register data cannot be read out.

The data transfer rate—in other words, the maximum SCLK frequency—depends on the MCLK pin clock. For

details, refer to the section “Switching characteristics.”

11. Master clock

The master clock frequency is 256fs. This clock signal must be input from the MCLK pin.

A frequency divider (1/2) incorporated so an input with a frequency of 512fs can also be supplied.

12. Audio data formats

I

BCLK and LRCLK. For details, refer to the section “Audio data formats.”