LC876D16A/08A

No.A1122-3/19

SIO

• SIO 0: 8-bit synchronous serial interface

1) LSB first/MSB first function available

2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)

3) Consecutive automatic data communication

(1 to 256 bits (communication available for each bit) (stop and reopening available for each byte)

• SIO 1: 8-bit asynchronous/synchronous serial interface

Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)

Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)

Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)

Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

AD Converter: 8 bits

× 8 channels

Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN)

• Noise rejection function

(Units of noise rejection filter: about 120

μs, when selecting a 32.768kHz crystal oscillator as a clock.)

• Supporting reception formats with a guide-pulse of half-clock/clock/none.

• Determines a end of reception by detecting a no-signal periods (No carrier).

(Supports same reception format with a different bit length.)

• X’tal HOLD mode release function

Watchdog Timer

• The watching timer period is set using an external RC.

• Watchdog timer can produce interrupt, system reset.

Clock Output Function

1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.

2) Able to output oscillation clock of sub clock.

System Clock Divider Function

• Able to reduce current consumption

Available minimum instruction cycle time: 300ns, 600ns, 1.2

μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs.

(Using 10MHz main clock)

Interrupts: 15 sources, 10 vectored interrupts

• Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,

an equal or lower priority interrupt request is refused.

• If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.

In the case of equal priority levels, the vector with the lowest address takes precedence.

No.

Vector

Selectable Level

Interrupt Signal

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/remote control receiver

4

0001BH

H or L

INT3/Base timer 0/1

5

00023H

H or L

T0H

6

0002BH

H or L

7

00033H

H or L

SIO0

8

0003BH

H or L

SIO1

9

00043H

H or L

ADC

10

0004BH

H or L

Port0/T4/T5

• Priority Level: X>H>L

• For equal priority levels, vector with lowest address takes precedence.

Subroutine Stack Levels: 512 levels Maximum (Stack is located in RAM.)