TSB43EA/EB/EC42

TI IEEE 1394a-2000

TSB43EA/EB/EC43

Consumer Electronics Solution

SLLA275A – April 2008 – Revised July 2008

Released – v1.1

PRODUCTION

DATA

Information

is

current

as

of

publication date. Products conform to specifications per the

terms of Texas Instruments standard warranty. Production

processing

does

not

necessarily

include

testing

of

all

parameters.

Copyright

2008, Texas Instruments Incorporated

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

5

3

Features

3.1

1394 Features

•

Integrated 400/200/100-Mbps 2-port/3-port PHY

•

Compliant with IEEE Std 1394-1995 and IEEE Std 1394a-2000

•

Supports bus manager functions and automatic 1394 self-id verification

•

Separate asynchronous acknowledgement (Ack) buffers decrease Ack-tracking burden

on external CPU

3.2

DTCP and AES Encryption Support for MPEG-DVB and DSS

(TSB43EA42/43 and TSB43EC42/43 Only)

•

DTCP encryption support on 1394 bus

•

AES128 encryption support on HSDI path (TSB43EC42/43 only)

•

Support for up to two encrypted/decrypted streams at one time

•

Full or restricted AKE performed with hardware assist

•

Secure method for loading DTCP and AES128 information using Ex-CPU interface

•

Localization support compliant with DTCP draft revision 1.51.

3.3

Video Interfaces

•

Two configurable high-speed data ports for video data

o

One port configurable as parallel or serial

o

One port serial only

•

Pass-through modes for HSDI0 and HSDI1

•

Packet Insertion – Two insertion buffers per HSDI for PAT, PMT, SIT, and DIT packets

•

PID filtering (32 PID filters per HSDI port)

3.4

External CPU Interfaces

•

Motorola 68K-style 16-bit asynchronous interface

•

SRAM-like 16-bit asynchronous interface

•

PCI interface (33 MHz) compliant to PCI specification version 3.0 (supports PCI slave

and master functions)

3.5

DMA

•

Higher asynchronous throughput with DMA hardware enhancements (available in PCI

mode only)

•

Internal DMA controller – Asynchronous, asynchronous Stream TX/RX

o

General DMA

o

Auto-response DMA for SBP2 transactions

3.6

Data Buffers

•

Two 4-KByte isochronous buffers for video data

•

Two 2-KByte asynchronous/asynchronous stream transmit buffers

•

Two 2-KByte asynchronous/asynchronous stream receive buffers

•

One 1-KByte self-ID buffer

•

Insertion buffers for MPEG-DVB/DSS packet insertion

•

Programmable data/space available indicators for buffer flow control