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TLK3134 Datasheet(PDF) 86 Page - Texas Instruments |
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TLK3134 Datasheet(HTML) 86 Page - Texas Instruments |
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86 / 150 page  TLK3134 4-Channel Multi-Rate Transceiver SLLS838D – MAY 2007 – REVISED JULY 2008 www.ti.com Table 2-147. TX1_DLL_CONTROL ADDRESS: 0x9401 DEFAULT: 0x0008 BIT(s) NAME DESCRIPTION ACCESS 4/5.37889.15 Lock_en For TI use only 4/5.37889.14 Write_en For TI use only 4/5.37889.13:8 Delay_sel[5:0] DLL delay control. For TI use only RW Phase shift control. Adds or removes delay element. Each delay element 4/5.37889.7:5 Offset[2:0] is 0.15ns. Refer Table 2-154: DLL Offset Control When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37889.3 Filter_en of the output clock. Table 2-148. TX2_DLL_CONTROL ADDRESS: 0x9402 DEFAULT: 0x0008 BIT(s) NAME DESCRIPTION ACCESS 4/5.37890.15 Lock_en For TI use only 4/5.37890.14 Write_en For TI use only 4/5.37890.13:8 Delay_sel[5:0] DLL delay control. For TI use only RW Phase shift control. Adds or removes delay element. Each delay element 4/5.37890.7:5 Offset[2:0] is 0.15ns. Refer Table 2-154: DLL Offset Control When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37890.3 Filter_en of the output clock. Table 2-149. TX3_DLL_CONTROL ADDRESS: 0x9403 DEFAULT: 0x0008 BIT(s) NAME DESCRIPTION ACCESS 4/5.37891.15 Lock_en For TI use only 4/5.37891.14 Write_en For TI use only 4/5.37891.13:8 Delay_sel[5:0] DLL delay control. For TI use only RW Phase shift control. Adds or removes delay element. Each delay element 4/5.37891.7:5 Offset[2:0] is 0.15 ns. Refer Table 2-154: DLL Offset Control When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37891.3 Filter_en of the output clock. Table 2-150. RX0_DLL_CONTROL ADDRESS: 0x9404 DEFAULT: 0x0008 BIT(s) NAME DESCRIPTION ACCESS 4/5.37892.15 Lock_en For TI use only 4/5.37892.14 Write_en For TI use only 4/5.37892.13:8 Delay_sel[5:0] DLL delay control. For TI use only RW Phase shift control. Adds or removes delay element. Each delay element 4/5.37892.7:5 Offset[2:0] is 0.15 ns. Refer Table 2-154: DLL Offset Control When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37892.3 Filter_en of the output clock. Detailed Description 86 Submit Documentation Feedback |
Similar Part No. - TLK3134_1 |
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Similar Description - TLK3134_1 |
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