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TLK3134 Datasheet(PDF) 84 Page - Texas Instruments |
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TLK3134 Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 150 page  TLK3134 4-Channel Multi-Rate Transceiver SLLS838D – MAY 2007 – REVISED JULY 2008 www.ti.com Table 2-142. HSTL_OUTPUT_SLEWRATE_CONTROL (continued) ADDRESS: 0x9301 DEFAULT: 0x0000 BIT(s) NAME DESCRIPTION ACCESS Slew Rate setting for output HSTL cells (for CH 0) 00 = No slew control (fastest edge) 4/5.37633.3:2 HSTL_SLEW_RATE_0 [1:0] 01 = 33% slew control RW 10 = 66 % slew control termination strength 11 = Full slew control (slowest edge) Table 2-143. HSTL_INPUT_VTP_CONTROL ADDRESS: 0x9302 DEFAULT: 0x0640 BIT(s) NAME DESCRIPTION ACCESS When set, increases NFET strength in all HSTL input cells. For TI 4/5.37634.15 I_FORCE_UP_N purposes Only When set, increases PFET strength in all HSTL input cells. For TI 4/5.37634.14 I_FORCE_UP_P purposes Only RW When set, decreases NFET strength in all HSTL input cells. For TI 4/5.37634.13 I_FORCE_DOWN_N purposes Only When set, decreases PFET strength in all HSTL input cells. For TI 4/5.37634.12 I_FORCE_DOWN_P purposes Only Drive strength control for HSTL input cells 3’b000 = 30 % drive strength increase 3’b001 = 20% drive strength increase 3’b010 = 10% drive strength increase 4/5.37634.11:9 I_VTP_DRIVE[2:0] 3’b011 = Normal drive strength (default) RW 3’b100 = 10% drive strength decrease 3’b101 = 20% drive strength decrease 3’b110 = 30% drive strength decrease 3’b111 = 40% drive strength decrease Filter Control 3’b000 = Impedance change filtering off 3’b001 = Update on 2 consecutive update requests 3’b010 = Update on 3 consecutive update requests(default) 4/5.37634.7:5 I_FILTER_CONTROL[2:0] 3’b011 = Update on 4 consecutive update requests RW 3’b100 = Update on 5 consecutive update requests 3’b101 = Update on 6 consecutive update requests 3’b110 = Update on 7 consecutive update requests 3’b111 = Update on 8 consecutive update requests Impedance Lock Control 4/5.37634.3 I_LOCK When set, disables dynamic impedance control updates for HSTL input RW cells Table 2-144. HSTL_OUTPUT_VTP_CONTROL ADDRESS: 0x9303 DEFAULT: 0x0640 BIT(s) NAME DESCRIPTION ACCESS When set, increases NFET strength in all HSTL output cells . For TI 4/5.37635.15 O_FORCE_UP_N purposes Only When set, increases PFET strength in all HSTL output cells . For TI 4/5.37635.14 O_FORCE_UP_P purposes Only RW When set, decreases NFET strength in all HSTL output cells . For TI 4/5.37635.13 O_FORCE_DOWN_N purposes Only When set, decreases PFET strength in all HSTL output cells . For TI 4/5.37635.12 O_FORCE_DOWN_P purposes Only Detailed Description 84 Submit Documentation Feedback |
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