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TL16C752CRHBRG4 Datasheet(PDF) 13 Page - Texas Instruments |
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TL16C752CRHBRG4 Datasheet(HTML) 13 Page - Texas Instruments |
13 / 50 page www.ti.com DMA Signaling TL16C752C DUAL UART WITH 64-BYTE FIFO SLLS646 – MARCH 2008 Figure 6. FIFO Polled Mode Operation There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1 multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time. Single DMA Transfers (DMA Mode0/FIFO Disable) Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has been loaded into it. Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty. Figure 7 shows TXRDY and RXRDY in DMA mode 0/FIFO disable. Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable Block DMA Transfers (DMA Mode1) Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the FIFO is full. Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7). Figure 8 shows TXRDY and RXRDY in DMA mode 1. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TL16C752C |
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