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HD64F7053F40 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HD64F7053F40 Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 919 page  Page Item Revisions (See Manual for Details) 400, 401 10.8 ATU-II Registers And Pins Table 10.4 ATU-II Registers and Pins Register names amended Pin names added and deleted 435 13.4.2 Compare Match Flag Set Timing Figure 13.4 CMF Set Timing CMCNT timing waveform amended 435 13.4.3 Compare Match Flag Clear Timing Description deleted 445 14.2.5 Serial Mode Register (SMR) Description amended 448 14.2.6 Serial Control Register (SCR) Description amended 456 14.2.8 Bit Rate Register (BRR) Description amended 463 14.2.9 Serial Direction Control Register (SDCR) Description amended 497 14.5.3 Break Detection and Processing 14.5.4 Sending a Break Signal Description added (Asynchronous Mode Only) 504 Table 15.2 HCAN Registers RFPR register name amended IMR initial value amended 510 15.2.3 Bit Configuration Register (BCR) BCR setting constraints amended Table note added 517 15.2.11 Interrupt Register (IRR) Initial value of bits 10 and 9 amended 519 Description of bit 9 amended 520 Description of bit 8 amended 533 15.3.1 Hardware Reset and Software Reset Description of Hardware Reset amended 537 Table 15.4 BCR Setting Limits Description amended 541 Figure 15.7 Transmission Flowchart Description amended 548 Figure 15.9 Reception Flowchart Description amended 552 Figure 15.11 HCAN Sleep Mode Flowchart Description amended 554 Figure 15.12 HCAN Halt Mode Flowchart Description amended 560 16.1.1 Features Description deleted |
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