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R5S72632P200FP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5S72632P200FP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 1862 page Rev. 2.00 Mar. 14, 2008 Page xi of xxxiv REJ09B0290-0200 5.4 Register Bank Errors.......................................................................................................... 129 5.4.1 Register Bank Error Sources................................................................................. 129 5.4.2 Register Bank Error Exception Handling ............................................................. 129 5.5 Interrupts............................................................................................................................ 130 5.5.1 Interrupt Sources................................................................................................... 130 5.5.2 Interrupt Priority Level ......................................................................................... 131 5.5.3 Interrupt Exception Handling ............................................................................... 132 5.6 Exceptions Triggered by Instructions ................................................................................ 133 5.6.1 Types of Exceptions Triggered by Instructions .................................................... 133 5.6.2 Trap Instructions ................................................................................................... 134 5.6.3 Slot Illegal Instructions ......................................................................................... 134 5.6.4 General Illegal Instructions................................................................................... 135 5.6.5 Integer Division Exceptions.................................................................................. 135 5.6.6 FPU Exceptions .................................................................................................... 136 5.7 When Exception Sources Are Not Accepted ..................................................................... 137 5.8 Stack Status after Exception Handling Ends...................................................................... 138 5.9 Usage Notes ....................................................................................................................... 140 5.9.1 Value of Stack Pointer (SP) .................................................................................. 140 5.9.2 Value of Vector Base Register (VBR) .................................................................. 140 5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 140 Section 6 Interrupt Controller (INTC) ...............................................................141 6.1 Features.............................................................................................................................. 141 6.2 Input/Output Pins ...............................................................................................................143 6.3 Register Descriptions ......................................................................................................... 144 6.3.1 Interrupt Priority Registers 01, 02, 05 to 17 (IPR01, IPR02, IPR05 to IPR17) .... 145 6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 147 6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 148 6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 149 6.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 150 6.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 152 6.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 153 6.3.8 Bank Control Register (IBCR).............................................................................. 154 6.3.9 Bank Number Register (IBNR) ............................................................................ 155 6.4 Interrupt Sources................................................................................................................ 156 6.4.1 NMI Interrupt........................................................................................................ 156 6.4.2 User Break Interrupt ............................................................................................. 156 6.4.3 H-UDI Interrupt .................................................................................................... 156 6.4.4 IRQ Interrupts ....................................................................................................... 156 6.4.5 PINT Interrupts ..................................................................................................... 157 |
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